Sense amplifiers are circuits used in reading data from storage transistors, i.e. core memory, in semiconductor memory arrays. One example of a known sense amplifier arrangement is shown in U.S. Pat. No. 5,198,997, to H. Arakawa, entitled "Ultraviolet Erasable Nonvolatile Memory". The arrangement shown in this patent is of particular interest in that it is directed toward a sense amplifier arrangement which includes a reference cell which is connected to the core memory sensing circuitry in another column through a current mirror arrangement.
FIG. 3 shows another sense amplifier arrangement according to the prior art, which differs from Arakawa. In particular, FIG. 3 shows a sense amplifier circuit 300 effective for detecting the conductive state of selected memory cells in the core memory of a selected semiconductor memory chip. The particular sense amplifier circuit 300 shown is a generally known approach applicable in particular to the field of variable threshold memory devices. The field of such devices includes the subfields of EPROMs, i.e., electrically programmable and ultra-violet (UV) erasable read only memories and EEPROMs, i.e., electrically programmable and electrically erasable read-only memories.
For purposes herein, and by convention, the conductive state of a memory cell containing a variable threshold device is defined as "low", if the cell is conductive or "on", and as "high", if the cell is non-conductive or "off".
The information regarding the conductive state of a particular core cell 310 in chip memory is transmitted by currents passing along a bit line 320 which is connected through several additional devices to a sense node 340 connected to the input side of one or more inverters 350, which amplify the voltages produced at sense node 340, in order to suitably drive an output device, not shown.
As is well known, core cell 310 may comprise one or more transistors; for example, core cell 310 may comprise a select transistor 311 connected at its drain to a bit line 320 and at its source to the drain of a variable threshold transistor 312 and driven at its gate by a word line 313, and a variable threshold transistor 312 driven at its gate by a sense line 314. A particular core cell is selected in read mode by applying appropriate bias voltages to word line 313 and sense line 314 and by turning on one or more core select transistors, such as core select transistor 321. Such a combination of bias conditions will effectively connect core cell 310 to a data bus 330, which acts as the core side input to sense amplifier 300. In addition, sense amplifier 300 has a reference side input line 430 which is additionally connected to a reference cell 410 similar to core cell 310. Reference cell 410 is driven at the gate of reference cell select transistor 411 by a reference cell select line 413, and at the gate of a reference cell variable threshold transistor 412 by a reference sense line 414.
The core side input of the sense amplifier, i.e., data bus 330, acts as inverting input to differential amplifier 333 and is also connected to the source of first pass transistor 331. The drain of first pass transistor 331 is connected to sense node 340, which in turn is connected to the source of second pass transistor 342, to the drain of current mirror transistor 341, to the input of amplifying inverter 350 and to the drain and gate of a clamping transistor 360.
The reference side input of the sense amplifier, i.e., reference data node 430, is connected to the source of third pass transistor 431. The drain of third pass transistor 431 is connected to reference node 440, which also connects to the gate and drain of a current mirror transistor 441, as well as to the gate of a current mirror transistor 341.
In addition, the non-inverting input of differential amplifier 333 is connected to a bias voltage source VB at node 332, the gate of first pass transistor 331 is connected to the output 334 of differential amplifier 333 and the gate of second pass transistor 342 is connected to the positive side 335 of bias voltage source VD, which in turn is connected at its negative side to output 334 of differential amplifier 333. In addition, clamping transistor 360 is connected at its source 370 to clamping voltage source VC.
In a practical implementation of this sense amplifier arrangement, the differential amplifier 333 and the various voltage supplies, VB, VD, and VC, would actually be implemented with a combination of transistors; they are shown here as ideal components for the purpose of explaining the operation of the sense amplifier.
Differential amplifier 333, in conjunction with bias voltage source VB, forces the voltage potential on data bus 330 to a controlled level effective for biasing the bit line connected terminal of the core cell. This bias approximately equals VB, with a typical value of ca. 2 V. The function of the first and second pass transistors 331 and 342 is to provide a current path for maintaining a voltage potential on data bus 330 equal to VB. If data bus 330 were discharged in the process of inquiring as to the status of a particular core cell, then the combination of first and second pass transistors 331 and 342 would provide a current path for restoring the voltage potential on data bus 330 approximately to VB. Voltage source VD provides an adequate drain-to-gate bias to keep first pass transistor 331 saturated under steady state bias conditions, i.e., when data bus 330 is charged up to a level essentially equal to VB. Thus, first pass transistor 331 will be maintained in an operational region in which the current is quadratically dependent on the gate-to-source bias, a condition favorable for operational faster response times by the circuit.
The function of third pass transistor 431 is to limit the voltage potential on reference data node 430 to a value essentially equal to the voltage potential on the data bus 330. This arrangement provides essentially similar drain bias conditions to both the selected core cell 310 as well as to reference cell 410. When applying appropriate bias voltages to reference cell select line 413 and to reference sense line 414, a current I.sub.REF flows through the reference cell. This reference current is mirrored via the two current mirror connected transistors 441 and 341 and is reflected at sense node 340 as the current I.sub.SENSE.
The various device sizes and bias levels are typically chosen in such a manner as to obtain a current I.sub.SENSE essentially equal to about one half of I.sub.CORE, where I.sub.CORE corresponds to the current of a "low" state core cell; thus, when reading the contents of a conductive cell, the sum of currents at sense node 340 would be such as to keep first and second pass transistors 331 and 342 in a conductive state and the voltage potential relatively low, while when reading a nonconductive cell, the sum of currents at sense node 340 will be such as to charge up the sense node to a higher voltage potential than that corresponding to the previously described conductive core cell case. The voltage potential at sense node 340 is limited at the lower end to a value close to VB+VD, as explained earlier, and the upper value is limited by the combination of clamping transistor 360 and clamping voltage source VC connected to the source of clamping transistor 360 at node 370. Reduced voltage swing at sense node 340 is desirable since it translates into reduced charge transfer and thus faster response time. Additionally, the trip point of inverter 350 should be above the lowest sense node potential, i.e., VB+VD, and below the highest sense node potential, as determined by clamping transistor 360 and clamping voltage source VC.
The arrangement described above senses the conductive state of the core cells. However, its performance is limited by several factors. By employing an individual, typically UV erased, reference cell associated with a sense amplifier in conjunction with a multitude of core cells programmed under varying voltage and temperature conditions, it is difficult to obtain optimum matching between the current of the reference cell, I.sub.REF, and the current of the core cell, I.sub.CORE, over a wide temperature and voltage range.
Further, when switching from reading a "high" state to reading a "low" state, data bus 330 starts out from being fully charged and has to be discharged just enough so that first pass transistor 331 will conduct a current somewhat larger than I.sub.SENSE, thus starting a downward movement of sense node 340. The voltage change required to turn on first pass transistor 331 is brought about by the fact that the conductive core cell must discharge the initially fully charged data bus 330. This is typically the limiting factor in response time, since the relatively small cell current "fights" the relatively large capacitive load of the data bus.
Additionally, while the clamping transistor 360 is meant to limit the voltage swing at sense node 340, it also adds capacitive loading which counteracts the benefit of reduced voltage swing.
Furthermore, since inverter 350 operates in a high gain region, it will present a relatively large capacitive load to sense node 340, due to inherent gate capacitance, as well as Miller reflected capacitance.
An object of the invention herein is accordingly to increase the speed of reading core memory by improving on or eliminating the limiting factors indicated above.